Careers
We are assembling a world-class talented, experienced and diversified team at our different locations to fuel our vision. This is to bring in cutting edge technologies with focus on highest performance. Our talent acquisition team is focusing on seeking the best for below positions to be a part of our team:
Current Open Positions:
Software
System Validation Engineer
Summary:
We are seeking a highly skilled and detail-oriented Engineer to join our team. The ideal candidate will be responsible for testing and validating the RDMA protocol in networking and storage solutions. The Engineer will collaborate with cross-functional teams to ensure that meets the required specifications for performance, reliability, and functionality.
Responsibilities:
Develop and implement test plans for Functional validation based on product requirements.
Define validation strategies, test cases, and procedures to ensure comprehensive coverage of functionality.
Conduct functional, performance, and reliability testing of systems.
Validate SoC features related to power management, system monitoring, and communication interfaces.
Validate PCIe features, including data transfer rates, link training, power management, and error handling.
Troubleshoot and analyse test results to identify and report issues.
Develop and maintain automated test scripts to streamline the SoC validation process.
Implement continuous integration and test automation frameworks to enhance efficiency.
Participate in the improvement of validation processes to enhance overall product quality.
Qualifications:
Proven experience as a System Validation Engineer or in a similar role.
Understanding of System-level testing, Operating System, Drivers, UEFI or BIOS fundamentals, IO interconnect and FW fundamentals.
Familiarity with various debug tools including emulators/JTAG-debuggers
Familiarity with industry standards and regulatory requirements for system validation.
Proficiency in C and scripting languages (e.g., Python, Shell) for test automation.
Excellent problem-solving and troubleshooting skills.
Strong communication and collaboration skills.
Preferred Skills:
Knowledge of industry standards BMC and System management.
Knowledge of protocols viz., PCIe (Peripheral Component Interconnect Express) & CXL, i2C and SPI.
Software Quality Engineer
Summary:
We are seeking a highly skilled and detail-oriented Engineer to join our team. The ideal candidate will be responsible for testing and validating the RDMA protocol in networking and storage solutions. The Engineer will collaborate with cross-functional teams to ensure that meets the required specifications for performance, reliability, and functionality.
Responsibilities:
Collaborate with development team to translate software requirements into high-quality test automation suites.
Conduct functional, performance, and reliability testing of RDMA components in networking and storage solutions.
Validate key RDMA features, including connection establishment, data transfer, congestion control, and error handling.
Utilize diagnostic tools and equipment for protocol analysis and debugging.
Collaborate with development team to test and validate features functionality.
Develop test strategy, test topology and test plan to validate the features end-to-end at scale with network security considerations.
Understand various customer deployments and solutions across data centre networks, security, routing and switching and validate customer profiles.
Execute test cases and validate the solution end-to-end and document the test results on performance, scale and security.
Debug and troubleshoot complex issues and work closely with the engineering team on the failures and validate the fixes.
Develop automation for the end-to-end solution validation and integrate the automation for seamless validation.
Qualifications:
Proven experience in RDMA validation or a related role.
Strong understanding of RDMA architecture, protocols, and technologies.
Excellent knowledge and hands-on experience in test plan development and validating scalable data centre network.
Hands-on experience in developing test automation suites.
Experience in performance, scale and convergence testing and analysing performance related issues and improving performance and convergence at system level.
Ability to develop and publish solution validation documents and test reports.
Strong verbal and written communication skills.
Preferred Skills:
Familiarity with RoCE (RDMA over Converged Ethernet) and other RDMA protocols.
Experience with InfiniBand technology.
Familiarity with storage protocols such as NVMe over Fabrics.
Understanding of server and data centre architectures.
Embedded System Developer With Platform Bring Up Experience
Summary:
We are seeking a highly skilled and detail-oriented Engineer to join our team. You will be part of an enthusiastic and energetic team involved in developing framework for embedded systems.
Responsibilities:
Design and develop Board Support Package (BSP) for OS.
Helping to develop, optimize and deliver the device driver and software needed, as well as helping Catalina Systems to grow in its role in new embedded and enterprise market segments.
Take initiative to improve features and processes.
Contribute ideas for product improvements and iterations.
Collaborate effectively with global software engineering teams.
Qualifications:
BTech / MTech degree (Computer Science, Computer/Electrical Engineering, or equivalent technical degree).
Solid understanding of software development methodology.
Expertise in ARM architecture know-how and assembly language programming.
Expertise in BareMetal / RTOS development experience in embedded C/C++ programming.
Hands-on experience in device driver and kernel level programming in RTOS / Linux.
Hands on experience in chip bring up.
Linux application development and debugging.
Excellent problem-solving and troubleshooting skills.
Strong communication and collaboration skills.
Preferred Skills:
Experience in firmware development with a very good understanding of Operating System concepts
Good working knowledge in C, Data Structures with Linux OS and Embedded RTOS/Kernels, User/Kernel Modules, Device Drivers, Porting and Integration of Platform SW Components
Familiarity with Open-Source embedded SW Development.
Development experience with Virtualization and Hypervisors including QEMU.
Hands-on programming experience with the Linux kernel internals, device drivers for multi-core SoCs.
Board bring-up in the area of PCIe sub-systems.
Hands-on programming and debugging experience with board bring-up and BSP delivery.
Good understanding of CPU architecture, ARM or X86, RISC-V.
Working knowledge of software and drivers for peripherals and controllers and services for complex SOC Systems) for ARM/Intel/PowerPC based)
Hands-on experience on Security solutions like Secure-boot, Root-of-Trust, Security Key Management (HSM)
Hands-on implementation with writing new PCIe or ethernet drivers in Linux
Porting an existing driver from one architecture to a different one.
Linux Kernel Memory, Clock, Timers, Interrupt sub-systems.
Good knowledge in PCIe/CXL/UCIe
U-Boot/UEFI and Linux in an embedded or server environment.
Understanding low level drivers like i2c, spi, GPIO, SDIO and UART as context menu.
System level debugging.
Hands on experience with FPGA or SOC bring up and related task.
System emulation software for the QEMU.
Network Application Parser Developer
Summary:
We are seeking a highly skilled and detail-oriented Engineer to join our team. You will be part of an enthusiastic and energetic team involved in developing framework for embedded systems.
Responsibilities:
Design and develop Network Parser for application protocols.
Helping to develop, optimize and deliver the device driver and software needed, as well as helping Catalina Systems to grow in its role in new embedded and enterprise market segments.
Take initiative to improve features and processes.
Contribute ideas for product improvements and iterations.
Collaborate effectively with global software engineering teams.
Qualifications:
BTech / MTech degree (Computer Science, Computer/Electrical Engineering, or equivalent technical degree).
Solid understanding of software development methodology.
Linux application development and debugging.
Excellent problem-solving and troubleshooting skills.
Strong communication and collaboration skills.
Preferred Skills:
C/C++: Minimum 5 years of hands-on coding experience.
Prior experience working in P4 programming language developing any data plane protocol(s) is required.
Working knowledge of Python and/or shell, Perl or any other scripting language.
Understanding of data structures and algorithms and ability to optimize those to support high scale architectures.
Working familiarity with network virtualization, network protocols and distributed systems.
Excellent troubleshooting, debugging and performance tuning skills for Linux based applications and kernel components, such as any prior experience using tools like oprofile and systems level performance debugging will be an advantage.
Proficiency with networking concepts and stack protocols including TCP/IP/UDP, RDMA, Ethernet etc. will be preferred.
Knowledge of software engineering best practices, source control, build, unit and integration testing process are desired.
Any experience with compiler stack with hands on experience with LLVM will be a plus. Ability to debug object code and understand instruction level working of the stack will be bonus.
Any prior experience with RISCV instruction set and working experience on RISCV platform will be a bonus.
Any prior experience where data plane packet parser implementation of any protocol from RFC/spec bonus will be bonus.
Kernel module development expertise will be a bonus.
Senior System Engineer
Summary:
The Senior Engineer - Sys position is an integral part of our team at Catalina systems.This role will be required to have a deep and broad technical competence to be able to design and development of well tested simulation QEMU models.This position is an opportunity for anyone who wants to expand their experiences into simulation and embedded systems.A simulator supports the definition, development, and deployment of digital systems.It is fast, accurate, scalable and extensible.
Responsibilities:
Developing QEMU device models.
Integrating device models into virtual systems.
Bring-up virtual systems.
QEMU to test specified scenarios.
Debugging and troubleshooting.
Lead the design & development of Qemu based virtual models for different hardware modules. Provide estimates to assist the planning.
Develop, port and test models for different modules like PCIE,SPI,SDCARD,I2C etc.
Qualifications:
Experience in firmware development with a very good understanding of Operating System concepts.
Good working knowledge in C, Data Structures with Linux OS and Embedded RTOS/Kernels, User/Kernel Modules, Device Drivers, Porting and Integration of Platform SW Components.
Familiarity with Open-Source embedded SW Development.
Good understanding of CPU architecture, ARM or X86,RISV.
Good knowledge in PCIe/CXL/UCIe.
Hands on experience with FPGA,SOC bring up and related task.
System level debugging..
System emulation software for the QEMU.
Preferred Skills:
Experience with simulation technologies is a plus. QEMU is preferred
Experience with VxWorks, Linux, U-Boot, UEFI, BIOS is desired.
Hardware
PCIe-CXL-Micro-Architect
Description:
Senior RTL Design Engineer with experience in Architecting/designing/integrating PCIe Root Complex, Host Bridge, Root Port, Address Translation Service and IOMMU for Server side PCIe Root Complex functionality. Ability to use IPs from standard vendors and Architect/Design any additional logic modules to be able to integrate with rest of the ASIC modules in the Server SoC ASICs. A thorough understanding of System level functionality and how PCIe/CXL Root Complex modules integrate with Cache-Coherent NoCs, Memory Subsystems, CPU complexes through AMBA bus protocols is required. Also, need to design and integrate CXL.io and CXL.mem functionality into the Root Complex and Root Port Modules by configuring the IPs from Standard Vendors like Synopsys.
Work with our design and verification teams spread across Armenia, India, China, and the backend/PR team located in China.
Consulting (full-time or part-time) or contracting to hire as a full-time or full-time hire.
ASAP to start from February 2024.
Compensation is based on expertise and experience.
DDR-Design-Engineer
Description:
Senior RTL design Engineer with Architecting/Integrating multi-channel DDR functionality into the high-performance Server SoC ASIC. Experience with integrating AMBA CHI/AXI based DDR4/DDR5/LPDDRx is required. The ability to pay attention to performance and latency is a must.
Work with our design and verification teams spread across Armenia, India, China, and the backend/PR team located in China.
Consulting (full-time or part-time) or contracting to hire as a full-time or full-time hire.
ASAP to start from February 2024.
Compensation is based on expertise and experience.
NoC-Micro-Architect
Description:
We will be integrating both Cache Coherent Interconnect NoC (CCI-NoC) and non-coherent Network-on-Chip (NC-NoC) IPs in our Server SoC ASIC.
Senior NoC system Architect/Design Engineer with prior experience in designing CCI-NoC including Snoop Filter, Home Agents and associated Caching modules is required. Ability to integrate AMBA bus protocols like CHI/ACE/ACE-Lite/AXI with the CCI-NoC, and design interface modules to connect with Interrupt Controllers, PCIe/CXL IO sub-systems, DDR/HBM Memory Sub-systems and other peripherals through NC-NoC is a must.
Work with our design and verification teams spread across Armenia, India, China, and the backend/PR team located in China.
Consulting (full-time or part-time) or contracting to hire as a full-time or full-time hire.
ASAP to start from February 2024.
Compensation is based on expertise and experience.
System SoC Architect
Description:
Experienced ASIC systems Architect to integrate all of the subsystems (PCIe/CXL IO Controllers and PHYs, Multi-Channel DDR5 Memory Controllers and PHYs, Cache-coherent NoC with Snoop Filter and Home Agents/nodes, Non-Coherent NoCs to connect to the low-speed IO and Micro-Controller, Interrupt Controller, UCIe Die-to-Die Controllers and PHYs, etc..), and drive the top-level design and validation at IOHub Chiplet-level.
Work with partners to integrate other chiplets, like CPU Chiplets and Domain Specific Accelerators at SoC level, and define RAS features at IOHub Chiplet level and SoC level.
Work with Platform SW team to define the system programming/debugging aspects of the IOHub Chiplet and System SoC.
Work with Back-end team for the P&R and layout aspects, provide support to Backend, and participate in the packaging discussions.
UVM Verification Lead
Description:
An RTL verification lead to lead the efforts to build UVM verification environment for our Server SoC ASIC. Collaborate with RTL design architects and verification engineers to define the higher-level architecture and define the entire verification environment. Work with verification engineers to implement and build the test bench(es) and test cases both at the ASIC sub-system level, ASIC Chip-level and System level.
Work with our design and verification teams spread across Armenia, India, China, and the backend/PR team located in China.
Consulting (full-time or part-time) or contracting to hire as a full-time or full-time hire.
ASAP to start from February 2024.
Compensation is based on expertise and experience.
Send Your Resume
Please send your resume along with the job title to our email address:
Email: careers@catalinasystems.io
Thank you for your interest!